The invention relates generally to memory devices, more particularly, to a multiple array memory device for high speed data access.
Many attempts have been made to maximize the speed of memory devices beyond the basic memory technology. Conventionally, high speed access is achieved by operating on an internal memory word within the device that is several times, typically two or four times, the external word width at the interface of the device. Therefore, when a memory read is requested, the device reads not only the requested data but also additional data that are not yet requested and holds those additional data in a buffer making them available for reduced time access if they are subsequently requested. The same technique is implemented for a write cycle in that when a memory write is requested, the device holds the write data in a buffer until several other data words have been written into the buffer. The device then updates the memory cells with the write data.
There are several disadvantages to the conventional device. First, the high speed access is limited to the internal word width. That is, if the internal word width is four times the external word width, the high speed access mode is valid for a maximum of four external words. Secondly, this type of device naturally creates address boundaries. That is, the high speed access mode is valid only for four external words that align with the larger internal words. Moreover, to efficiently use the high speed access mode, the starting and ending addresses of external words must be aligned with the address of the internal word. Such alignment requires additional internal circuitry to count addresses and/or roll the addresses over to the least significant address in the internal word when the most significant address in the internal word is reached.
Early memory systems used cabinet technology in which several cabinets each containing a section of memory are connected. In operation, data could be input into or output from one cabinet while other cabinets were being accessed. Thus, access time could be reduced. However, this arrangement was too bulky and impractical. Additionally, such an arrangement was a distinct memory system composed of many devices of singular architecture forming a different overall architecture and not a single memory architecture nor a single chip architecture.
A high speed memory device of single architecture that allows faster access of data than the process technology inherently permits without the disadvantages described above is thus needed.